1. Field of the Invention
The present invention relates to a D-type flip-flop circuit, and more particularly to a flip-flop circuit which is a combination of logical gates used in a semiconductor integrated circuit and which takes in a data input in synchronism with a clock input, updates an output in accordance with the content of the data input and holds the output until the next update time.
2. Related Background Art
A prior art D-type flip-flop circuit of this type is shown in FIG. 1. It comprises six NOR gates 1-6. It takes in a data input D at a timing of a clock input CLK and transfers it to outputs Q and Q. Of the NOR gates 1-6, the NOR gates 1-4 form a data take-in circuit 7, and the NOR gates 5 and 6 form a data hold circuit 8. The data take-in circuit 7 takes in the data input D at the timing synchronized with the clock input CLK. The data hold circuit 8 holds the data outputs Q and Q determined by the content of the data input D taken in by the data take-in circuit 7 until the next data take-in time which is synchronized with the clock input.
In the prior art circuit, the data must pass through the data take-in circuit 7 and the data hold circuit 8 in sequence after the clock input CLK changes to cause the data input take-in timing and a delay occurs before the output is set in accordance with the data input. As a result, the operation speed is low because of the delay times involved.